? semiconductor components industries, llc, 2014 august, 2014 ? rev. 9 1 publication order number: mc74hc4316a/d mc74hc4316a quad analog switch/ multiplexer/demultiplexer with separate analog and digital power supplies high?performance silicon?gate cmos the mc74hc4316a utilizes silicon?gate cmos technology to achieve fast propagation delays, low on resistances, and low off?channel leakage current. this bilateral switch/multiplexer/ demultiplexer controls analog and digital voltages that may vary across the full analog power?supply range (from v cc to v ee ). the hc4316a is similar in function to the metal?gate cmos mc14016 and mc14066, and to the high?speed cmos hc4066a. each device has four independent switches. the device control and enable inputs are compatible with standard cmos outputs; with pullup resistors, they are compatible with lsttl outputs. the device has been designed so that the on resistances (r on ) are much more linear over input voltage than r on of metal?gate cmos analog switches. logic?level translators are provided so that the on/off control and enable logic?level voltages need only be v cc and gnd, while the switch is passing signals ranging between v cc and v ee . when the enable pin (active?low) is high, all four analog switches are turned off. features ? logic?level t ranslator for on/off control and enable inputs ? fast switching and propagation speeds ? high on/off output voltage ratio ? diode protection on all inputs/outputs ? analog power?supply voltage range (v cc ? v ee ) = 2.0 to 12.0 v ? digital (control) power?supply voltage range (v cc ? gnd) = 2.0 v to 6.0 v, independent of v ee ? improved linearity of on resistance ? chip complexity: 66 fets or 16.5 equivalent gates ? nlv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable* ? these devices are pb?free, halogen free and are rohs compliant http://onsemi.com marking diagram soic?16 d suffix case 751b 1 16 hc4316ag awlyww a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g = pb?free package device package shipping ? ordering information ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specification s brochure, brd8011/d. soic?16 (pb?free) mc74hc4316adr2g 2500/ tape&reel soic?16 (pb?free) nlv74hc4316adr2g* 2500/ tape&reel 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 y d x d d on/off control a on/off control v cc v ee x c y c x b y b y a x a gnd enable c on/off control b on/off control pin assignment
mc74hc4316a http://onsemi.com 2 function table inputs state of analog switch enable on/off control l l h h l x on off off x = don?t care. figure 1. logic diagram x a a on/off control analog switch level translator analog outputs/inputs pin 16 = v cc pin 8 = gnd pin 9 = v ee gnd v ee 2 y a 1 15 x b b on/off control analog switch level translator 3 y b 4 5 x c c on/off control analog switch level translator 11 y c 10 6 x d d on/off control analog switch level translator 12 y d 13 14 enable 7 analog inputs/outputs = x a , x b , x c , x d figure 2. on resistance test set?up plotter mini computer programmable power supply dc analyzer v cc + - analog in common out gnd device under test v ee
mc74hc4316a http://onsemi.com 3 maximum ratings symbol parameter value unit v cc positive dc supply voltage (ref. to gnd) (ref. to v ee ) ?0.5 to +7.0 ?0.5 to +14.0 v v ee negative dc supply voltage (ref. to gnd) ?7.0 to +0.5 v v is analog input voltage v ee ? 0.5 to v cc + 0.5 v v in dc input voltage (ref. to gnd) ?0.5 to v cc + 0.5 v i dc current into or out of any pin 25 ma p d power dissipation in still air soic package* 500 mw t stg storage temperature ? 65 to + 150 c t l lead temperature, 1 mm from case for 10 seconds) 260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. *derating ? soic package: ?7 mw/ c from 65 to 125 c recommended operating conditions symbol parameter min max unit v cc positive dc supply voltage (ref. to gnd) 2.0 6.0 v v ee negative dc supply voltage (ref. to gnd) ?6.0 gnd v v is analog input voltage v ee v cc v v in digital input voltage (ref. to gnd) gnd v cc v v io * static or dynamic voltage across switch ? 1.2 v t a operating temperature, all package types ?55 +125 c t r , t f input rise and fall time v cc = 2.0 v (control or enable inputs) v cc = 3.0 v (figure 10) v cc = 4.5 v v cc = 6.0 v 0 0 0 0 1000 600 500 400 ns functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. *for voltage drops across the switch greater than 1.2 v (switch on), excessive v cc current may be drawn; i.e., the current out of the switch may contain both v cc and switch input components. the reliability of the device will be unaffected unless the maximum ratings are exceeded. dc electrical characteristics digital section (voltages referenced to gnd) v ee = gnd except where noted symbo l parameter test conditions v cc v guaranteed limit unit ?55 to 25 c 85 c 125 c v ih minimum high?level voltage, control or enable inputs r on = per spec 2.0 3.0 4.5 6.0 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 v v il maximum low?level voltage, control or enable inputs r on = per spec 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 v i in maximum input leakage current, control or enable inputs v in = v cc or gnd v ee = ?6.0 v 6.0 0.1 1.0 1.0 a i cc maximum quiescent supply current (per package) v in = v cc or gnd v io = 0 v v ee = gnd v ee = ?6.0 6.0 6.0 2 4 20 40 40 160 a this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high?impedance cir- cuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open. i/o pins must be connected to a properly terminated line or bus.
mc74hc4316a http://onsemi.com 4 dc electrical characteristics analog section (voltages referenced to v ee ) symbo l parameter test conditions v cc v v ee v guaranteed limit unit ?55 to 25 c 85 c 125 c r on maximum ?on? resistance v in = v ih v is = v cc to v ee i s 2.0 ma (figure 2) 2.0* 4 5 4.5 6.0 0.0 0.0 ?4.5 ?6.0 ? 160 90 90 ? 200 110 110 ? 240 130 130 v in = v ih v is = v cc or v ee (endpoints) i s 2.0 ma (figure 2) 2.0 4.5 4.5 6.0 0.0 0.0 ?4.5 ?6.0 ? 90 70 70 ? 115 90 90 ? 140 105 105 r on maximum difference in ?on? resistance between any two channels in the same package v in = v ih v is = 1/2 (v cc ? v ee ) i s 2.0 ma 2.0 4.5 4.5 6.0 0.0 0.0 ?4.5 ?6.0 ? 20 15 15 ? 25 20 20 ? 30 25 25 i off maximum off?channel leakage current, any one channel v in = v il v io = v cc or v ee switch off (figure 3) 6.0 ?6.0 0.1 0.5 1.0 a i on maximum on?channel leakage current, any one channel v in = v ih v is = v cc or v ee (figure 4) 6.0 ?6.0 0.1 0.5 1.0 a *at supply voltage (v cc ? v ee ) approaching 2.0 v the analog switch?on resistance becomes extremely non?linear. therefore, for low?voltage operation, it is recommended that these devices only be used to control digital signals. ac electrical characteristics (c l = 50 pf, control or enable t r = t f = 6 ns, v ee = gnd) symbo l parameter v cc v guaranteed limit unit ?55 to 25 c 85 c 125 c t plh , t phl maximum propagation delay, analog input to analog output (figures 8 and 9) 2.0 4.5 6.0 40 6 5 50 8 7 60 9 8 ns t plz , t phz maximum propagation delay, control or enable to analog output (figures 10 and 11) 2.0 4.5 6.0 130 40 30 160 50 40 200 60 50 ns t pzl , t pzh maximum propagation delay, control or enable to analog output (figures 10 and 11) 2.0 4.5 6.0 140 40 30 175 50 40 250 60 50 ns c maximum capacitance on/off control and enable inputs ? 10 10 10 pf control input = gnd analog i/o feedthrough ? ? 35 1.0 35 1.0 35 1.0 c pd power dissipation capacitance (per switch) (figure 13)* typical @ 25 c, v cc = 5.0 v pf 15 *used to determine the no?load dynamic power consumption: p d = c pd v cc 2 f + i cc v cc .
mc74hc4316a http://onsemi.com 5 additional application characteristics (gnd = 0 v) symbol parameter test conditions v cc v v ee v limit* 25 c unit bw maximum on?channel bandwidth or minimum frequency response (figure 5) f in = 1 mhz sine wave adjust f in voltage to obtain 0 dbm at v os increase f in frequency until db meter reads ?3 db r l = 50 , c l = 10 pf 2.25 4.50 6.00 ?2.25 ?4.50 ?6.00 150 160 160 mhz ? off?channel feedthrough isolation (figure 6) f in sine wave adjust f in voltage to obtain 0 dbm at v is f in = 10 khz, r l = 600 , c l = 50 pf 2.25 4.50 6.00 ?2.25 ?4.50 ?6.00 ?50 ?50 ?50 db f in = 1.0 mhz, r l = 50 , c l = 10 pf 2.25 4.50 6.00 ?2.25 ?4.50 ?6.00 ?40 ?40 ?40 ? feedthrough noise, control to switch (figure 7) v in 1 mhz square wave (t r = t f = 6 ns) adjust r l at setup so that i s = 0 a r l = 600 , c l = 50 pf 2.25 4.50 6.00 ?2.25 ?4.50 ?6.00 30 65 100 mv pp r l = 10 k , c l = 10 pf 2.25 4.50 6.00 ?2.25 ?4.50 ?6.00 60 130 200 ? crosstalk between any two switches (figure 12) f in sine wave adjust f in voltage to obtain 0 dbm at v is f in = 10 khz, r l = 600 , c l = 50 pf 2.25 4.50 6.00 ?2.25 ?4.50 ?6.00 ?70 ?70 ?70 db f in = 1.0 mhz, r l = 50 , c l = 10 pf 2.25 4.50 6.00 ?2.25 ?4.50 ?6.00 ?80 ?80 ?80 thd total harmonic distortion (figure 14) f in = 1 khz, r l = 10 k , c l = 50 pf thd = thd measured ? thd source v is = 4.0 v pp sine wave v is = 8.0 v pp sine wave v is = 11.0 v pp sine wave 2.25 4.50 6.00 ?2.25 ?4.50 ?6.00 0.10 0.06 0.04 % *limits not tested. determined by design and verified by qualification.
mc74hc4316a http://onsemi.com 6 figure 3. maximum off channel leakage current, any one channel, test set?up figure 4. maximum on channel leakage current, test set?up off 16 v cc v ee a v cc v ee v cc o/i 7 8 9 selected control input v il on 16 v cc n/c a v ee v cc v ee 7 8 9 selected control input v ih figure 5. maximum on?channel bandwidth test set?up on 16 v cc 0.1 f c l * f in to db meter *includes all probe and jig capacitance. r l r l v ee 7 8 9 selected control input v cc figure 6. off?channel feedthrough isolation, test set?up off 16 v cc 0.1 f c l * f in to db meter *includes all probe and jig capacitance. r l v ee 7 8 9 selected control input r l v cc figure 7. feedthrough noise, control to analog out, test set?up 16 v cc *includes all probe and jig capacitance. on/off control r l selected control input v ee 7 8 9 c l * test point r l v cc gnd analog in analog out 50% t plh t phl 50% figure 8. propagation delays, analog in to analog out v is
mc74hc4316a http://onsemi.com 7 positionwhen testing t plz and t pzl figure 9. propagation delay test set?up on 16 v cc *includes all probe and jig capacitance. test point analog o/i analog i/o 50 pf* selected control input v cc figure 10. propagation delay, on/off control to analog out on/off v cc test point 16 v cc 1 k positionwhen testing t phz and t pzh 50 pf* 1 2 1 2 figure 11. propagation delay test set?up 1 2 figure 12. crosstalk between any two switches, test set?up (adjacent channels used) r l on 16 *includes all probe and jig capacitance. off r l v is f in 0.1 f figure 13. power dissipation capacitance test set?up 16 v cc n/c on/off a n/c selected control input control on 16 v cc 10 f c l * f in r l to distortion meter *includes all probe and jig capacitance. v os v is selected control input v cc figure 14. total harmonic distortion, test set?up 7 8 9 *includes all probe and jig capacitance. 8 9 control or enable v cc 7 8 9 v ee c l * c l * r l selected control input v cc test point analog i/o 7 8 9 v ee 7 8 9 v ee 50% 50% 90% 10% t pzl t plz t pzh t phz high impedance v ol v oh high impedance v cc gnd 50% analog out control enable t r t f
mc74hc4316a http://onsemi.com 8 applications information 0 -10 -20 -30 -40 -50 - 100 1.0 2.0 frequency (khz) dbm -60 -70 -80 -90 fundamental frequency device source figure 15. plot, harmonic distortion 3.0 the enable and control pins should be at v cc or gnd logic levels, v cc being recognized as logic high and gnd being recognized as a logic low. unused analog inputs/outputs may be left floating (not connected). however, it is advisable to tie unused analog inputs and outputs to v cc or v ee through a low value resistor. this minimizes crosstalk and feedthrough noise that may be picked up by the unused i/o pins. the maximum analog voltage swings are determined by the supply voltages v cc and v ee . the positive peak analog voltage should not exceed v cc . similarly, the negative peak analog voltage should not go below v ee . in the example below, the difference between v cc and v ee is 12 v. therefore, using the configuration in figure 16, a maximum analog signal of twelve volts peak?to?peak can be controlled. when voltage transients above v cc and/or below v ee are anticipated on the analog channels, external diodes (dx) are recommended as shown in figure 17. these diodes should be small signal, fast turn?on types able to absorb the maximum anticipated current surges during clipping. an alternate method would be to replace the dx diodes with mosorbs (mosorb ? is an acronym for high current surge protectors). mosorbs are fast turn?on devices ideally suited for precise dc protection with no inherent wear out mechanism. analog o/i on 16 v cc = 6 v analog i/o + 6 v -6 v + 6 v -6 v enable control inputs (v cc or gnd) on 16 v cc d x d x v cc d x figure 16. figure 17. transient suppressor application 8 selected control input d x selected control input + 6 v v ee -6 v v cc v ee enable control inputs (v cc or gnd) v ee v ee
mc74hc4316a http://onsemi.com 9 v cc = 5 v 16 hc4316a enable and control inputs 8 5 6 14 15 ttl analog signals r* analog signals hct buffer r* = 2 to 10 k channel 4 channel 3 channel 2 channel 1 1 of 4 switches common i/o 1234 control inputs input output 0.01 f lf356 or equivalent a. using pull?up resistors b. using hct buffer figure 18. lsttl/nmos to hcmos interface figure 19. switching a 0?to?12 v signal using a single power supply (gnd 0 v) figure 20. 4?input multiplexer figure 21. sample/hold amplifier + - 1 of 4 switches +5 v 16 hc4016a control inputs 7 5 6 14 15 lsttl/ nmos analog signals analog signals 1 of 4 switches 1 of 4 switches 1 of 4 switches 7 r* r* r* r* v ee = 0 to -6 v 9 v ee = 0 to -6 v 9 12 v power supply r 1 = r 2 r 1 r 2 v cc = 12 v v ee = 0 v gnd = 6 v 12 v pp analog input signal c r 3 r 4 v cc v ee 1 of 4 switches analog output signal 12 v 0 r 1 = r 2 r 3 = r 4
mc74hc4316a http://onsemi.com 10 package dimensions soic?16 case 751b?05 issue k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ?b? ?a? m 0.25 (0.010) b s ?t? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 6.40 16x 0.58 16x 1.12 1.27 dimensions: millimeters 1 pitch soldering footprint* 16 89 8x *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 mc74hc4316a/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. mosorb is a registered trademark of semiconductor components industries, llc (scillc).
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